This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large host computers and servers (collectively referred to herein as xe2x80x9chost computer/serversxe2x80x9d) require large capacity data storage systems. These large computer/servers generally includes data processors, which perform many operations on data introduced to the host computer/server through peripherals including the data storage-system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the host computer/server are coupled together through an interface. The interface includes xe2x80x9cfront endxe2x80x9d or host computer/server controllers (or directors) and xe2x80x9cback-endxe2x80x9d or disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the host computer/server. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the host computer/server merely thinks it is operating with its own local disk drive. One such system is described in U.S. Pat. No. 5,206,939, entitled xe2x80x9cSystem and Method for Disk Mapping and Data Retrievalxe2x80x9d, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the host computer/server controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the host computer/server before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the host computer/server. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The host computer/server controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. The host computer/server controllers are mounted on host computer/server controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk directors, host computer/server directors, and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a director, the backplane printed circuit board has a pair of buses. One set the disk directors is connected to one bus and another set of the disk directors is connected to the other bus. Likewise, one set the host computer/server directors is connected to one bus and another set of the host computer/server directors is directors connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
The arrangement is shown schematically in FIG. 1. Thus, the use of two buses B1, B2 provides a degree of redundancy to protect against a total system failure in the event that the controllers or disk drives connected to one bus, fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus. Thus, in operation, when the host computer/server 12 wishes to store data, the host computer 12 issues a write request to one of the front-end directors 14 (i.e., host computer/server directors) to perform a write command. One of the front-end directors 14 replies to the request and asks the host computer 12 for the data. After the request has passed to the requesting one of the front-end directors 14, the director 14 determines the size of the data and reserves space in the cache memory 18 to store the request. The front-end director 14 then produces control signals on one of the address memory busses B1, B2 connected to such front-end director 14 to enable the transfer to the cache memory 18. The host computer/server 12 then transfers the data to the front-end director 14. The front-end director 14 then advises the host computer/server 12 that the transfer is complete. The front-end director 14 looks up in a Table, not shown, stored in the cache memory 18 to determine which one of the back-end directors 20 (i.e., disk directors) is to handle this request. The Table maps the host computer/server 12 addresses into an address in the bank 14 of disk drives. The front-end director 14 then puts a notification in a xe2x80x9cmail boxxe2x80x9d (not shown and stored in the cache memory 18) for the back-end director 20, which is to handle the request, the amount of the data and the disk address for the data. Other back-end directors 20 poll the cache memory 18 when they are idle to check their xe2x80x9cmail boxesxe2x80x9d. If the polled xe2x80x9cmail boxxe2x80x9d indicates a transfer is to be made, the back-end director 20 processes the request, addresses the disk drive in the bank 22, reads the data from the cache memory 18 and writes it into the addresses of a disk drive in the bank 22.
When data is to be read from a disk drive in bank 22 to the host computer/server 12 the system operates in a reciprocal manner. More particularly, during a read operation, a read request is instituted by the host computer/server 12 for data at specified memory locations (i.e., a requested data block). One of the front-end directors 14 receives the read request and examines the cache memory 18 to determine whether the requested data block is stored in the cache memory 18. If the requested data block is in the cache memory 18, the requested data block is read from the cache memory 18 and is sent to the host computer/server 12. If the front-end director 14 determines that the requested data block is not in the cache memory 18 (i.e., a so-called xe2x80x9ccache missxe2x80x9d) and the director 14 writes a note in the cache memory 18 (i.e., the xe2x80x9cmail boxxe2x80x9d) that it needs to receive the requested data block. The back-end directors 20 poll the cache memory 18 to determine whether there is an action to be taken (i.e., a read operation of the requested block of data). The one of the back-end directors 20 which poll the cache memory 18 mail box and detects a read operation reads the requested data block and initiates storage of such requested data block stored in the cache memory 18. When the storage is completely written into the cache memory 18, a read complete indication is placed in the xe2x80x9cmail boxxe2x80x9d in the cache memory 18. It is to be noted that the front-end directors 14 are polling the cache memory 18 for read complete indications. When one of the polling front-end directors 14 detects a read complete indication, such front-end director 14 completes the transfer of the requested data which is now stored in the cache memory 18 to the host computer/server 12.
The use of mailboxes and polling requires time to transfer data between the host computer/server 12 and the bank 22 of disk drives thus reducing the operating bandwidth of the interface.
In accordance with the present invention, a memory system is provided having a common memory region. The memory region includes a pair of control ports and a common DATA port. A switching network is provided having a pair of information ports, for: coupling information having a control portion and a DATA portion between: a first one of such pair of information ports; and, a first one of the control ports and the DATA port through a first switch section; and coupling information having a control portion and a DATA portion between: a second one information ports; and, a second one of the control ports and the DATA port though a second switch section. A pair of clocks is included. A first one of such clocks is fed to operate the first switch section in coupling the information through such first section and a second one of such clocks being fed to operate the second switch section in coupling the information through such first section.
In one embodiment, the memory system includes: (A) a memory array region for storing information, such memory array region having: (a) a DATA port; (b) a pair of memory control ports; (B) a pair of logic sections, each one thereof having: (a) a logic section control port connected to a corresponding one of the pair of memory control ports for providing memory control signals to the memory array region, and, (b) a logic section DATA port, and (c) wherein the logic section DATA ports of the pair of logic sections are connected together and to the memory array DATA port; and, (C) a pair of independent clocks, each one of such clocks being coupled to a corresponding one of the logic sections to provide clock signals to such one of the logic sections.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
These and other features of the invention will become more readily apparent from the following detailed description when read together with the accompanying drawings, in which:
FIG. 1 is a block diagram of a data storage system according to the PRIOR ART;
FIG. 2 is a block diagram of a data storage system according to the invention;
FIG. 2A shows the fields of a descriptor used in the system interface of the data storage system of FIG. 2;
FIG. 2B shows the filed used in a MAC packet used in the system interface of the data storage system of FIG. 2;
FIG. 3 is a sketch of an electrical cabinet storing a system interface used in the data storage system of FIG. 2;
FIG. 4 is a diagramatical, isometric sketch showing printed circuit boards providing the system interface of the data storage system of FIG. 2;
FIG. 5 is a block diagram of the system interface used in the data storage system of FIG.2;
FIG. 6 shows the relationship between FIGS. 6A and 6B which when taken together is a block diagram showing the connections between front-end and back-end directors to one of a pair of message network boards used in the system interface of the data storage system of FIG. 2;
FIG. 7 is a block diagram of an exemplary one of the director boards used in the system interface of he data storage system of FIG. 2;
FIG. 8 is a block diagram of the system interface used in the data storage system of FIG. 2;
FIG. 8A is a diagram of an exemplary global cache memory board used in the system interface of FIG. 8;
FIG. 8B is a diagram showing a pair of director boards coupled between a pair of host processors and global cache memory boards used in the system interface of FIG. 8;
FIGS. 9A, 9B and 9C are a more detailed block diagram of the exemplary cache memory board of FIG. 8A;
FIG. 10 is a block diagram of a crossbar switch used in the memory board of FIGS. 9A, 9B and 9C;
FIGS. 11A, 11B, 11C and 11D are a block diagram of an upper port interface section used in the crossbar switch of FIG. 10;
FIGS. 12A, 12B, 12C and 12D are a block diagram of a lower port interface section used in the crossbar switch of FIG. 10;
FIGS. 13A, 13B, 13C, 13D and 13E are a block diagram of a pair of logic sections used in the memory board of FIGS. 9A, 9B and 9C;
FIGS. 14A, 14B, 14C and 14D are a block diagram of a pair of port controllers used in the pair of logic sections of FIGS. 13A, 13B, 13C, 13D and 13E;
FIGS. 15A, 15B, 15C, 15D and 15E are a block diagram of a pair of arbitration logics used in the pair of logic sections of FIGS. 13A, 13B, 13C, 13D and 13E and of a watchdog section used for such pair of logic sections;
FIG. 16 is a diagram showing words that make up exemplary information cycle used in the memory board of FIGS. 9A, 9B and 9C;
FIG. 17 is a Truth Table for a majority gate used in the memory board of FIGS. 9A, 9B and 9C;
FIG. 18 is a block diagram shown interconnections between one of the arbitration units used in one of the pair of port controllers of FIGS. 13A, 13B, 13C, 13D and 13E and a filter used in the arbitration unit of the other one of such pair of controllers of FIGS. 13A, 13B, 13C, 13D and 13E;
FIG. 19 is a timing diagram of signals in arbitration units of FIG. 18 used of one of the pair of port controllers of FIGS. 14A, 14B, 14C and 14D and a filter used in the arbitration unit used in the other one of such pair of controllers of FIGS. 14A, 14B, 14C and 14D; and
FIGS. 20A, 20B and 20C are a more detailed block diagram of arbitrations used in the arbitration logics of FIGS. 15A, 15B, 15C, 15D and 15E.